After the first CES keynote in the (almost) 50 year history of AMD, the dust settles. AMD announced the industry first 7 nm graphics card, the Radeon 7 and shedded some light on their upcoming Zen 2 based 7 nm x86 cpus, also an industry first.
Let’s dig a little deeper and analyse these new Zen 2 snippets and what this could mean for AMD’s future processor strategy.
A strategy of chiplets
Achieving solid speed increases for processors has become harder and harder every year. Up until Ryzen we saw only modest speed increases from the x86 processor monopolist. But, with the launch of AMD’s Ryzen, a multi-core war was initiated. AMD’s 8 and 16 core Ryzen and Threadripper cpus triggered the release of multiple new chip designs from Intel, but ultimately could not match the 32 core Threadripper (HEDT) and 32 core Epyc enterprise server chips.
Adding more cores has its limits as thermal dissipation, fast memory access and inter-core communication become increasingly difficult. That is why a manufacturing or lithography node shrink is needed. It generally means less power hungry products, which can be clocked higher for an increase in performance at the same energy usage.
However, not all parts of a cpu can gain equally from node shrink. Parts that communicate with memory for example will gain less as they have a specific speed with which they communicate with memory.
Innovative use of limited resources
Developing a new cpu on a cutting edge process is very expensive (industry watchers talk about ~300 million). This is why AMD decided to split the cpu up into multiple parts. One part takes care of computation (the Zen 2 chiplet) and another part manages communication of the chiplets with each other and the rest of the system (the IO die). The tradeoff to this newly attained flexibility could be lower peak performance, because of the extra latency of communicating from one part to another. However, in previous high core count HEDT cpus, communication of the cpus without memory access was routed through the cpus which did have memory access. Resulting in lower peak performance for the complete package.
This time AMD took a different approach. Flexibility increases by handing over all communication to a specialised IO die. And performance increases thanks to the node shrink which enables higher clock speeds for the chiplets.
In this new design, the IO die takes care of all housekeeping tasks like communication to memory and other cpu sockets. The x86 compute chiplet takes care of all computations. The main positive of using a IO die with compute chiplets is that one can support much, much more cores.
Cores, cores, cores!
This makes perfect sense for enterprise server and cloud applications. More (high performance) cores per socket will result in less power usage and fewer servers needed. We already know from the Next Horizon event in November last year that the next generation of Epyc cpus will support up to 64 cores and a mind boggling 128 threads.
For Threadripper, AMDs high end desktop line, we expect 64 cores maximum as the cpus are comparable in size to the Epyc 2 series. Performance of high core count cpus will increase compared to the previous generation because of reduced latency in memory intensive applications.
While only a 8 core chip was demoed during the keynote, it is very likely that cpus with more cores are coming in the future. It was very clear that the engineering sample held up by dr. Lisa Su had exactly enough space for another compute chiplet. We expect that a 16 cores and 32 threads AM4 Ryzen desktop chips are technically feasible and are on the roadmap. But we expect AMD to release parts with less cores first, as those are the bread and butter chips for AMD. Probably also to keep HEDT sales on a decent level until new 7 nm Threadrippers can be released.
Different IO dies
The pictures above makes clear that the IO dies of the Epyc and Ryzen desktop chip are not the same size. Epyc’s IO die is about 3,5 times larger as the IO die seen on Ryzen. This makes obvious sense, as Epyc has more chiplets and memory channels to support.
By producing the specialised parts on the least expensive node, AMD will save on production costs. Later, when the production costs of 7nm have dropped or when new nodes sizes become available, AMD can decide to switch the IO dies to a smaller process as well.
There is speculation if this IO die will also support other types of chips like a gpu or AI accelerator. Marrying the Zen based x86 compute die with these parts via the IO die will give AMD access to new flexibility to create truly custom and special purpose chips for a multitude of industries.
Previous and current generation Epyc and Threadripper processors use up to two dummy dies. The chip uses the dummy die to properly support the heat-spreader of the very large chips.
The engineering sample held up by dr. Su in the keynote clearly showed only a single Zen 2 die. While this could mean that an asymmetrical distribution of the dies is possible, it is much more likely that the final chip will contain an IO die with two Zen 2 chiplets. This way, AMD can use cpus with up to 4 defective cores. A measure to maximise yield and therefore keep the production costs down.
What about mobile?
During the CES keynote, AMD disclosed no details about future Zen 2 based mobile parts. And this is unlikely to change in the near future, as AMD released 3000 series Ryzen Mobile chips at the start of the CES event.
For Zen 2 based Ryzen Mobile chips there are two possible scenarios. Either AMD has a special IO die optimised for mobile. Which would make the chip large and maybe less suitable for ultra-thin notebooks. Or, AMD will use a single 7 nm chiplet with the bare minimum built-in support for RAM and peripherals. No concrete hints about the Ryzen Mobile cpus have surfaced yet, so we can only speculate about this. But, as power usage is the main concern for laptops, this last possibility would make perfect sense.
We expect a Zen 2 based Ryzen Mobile offering to have a maximum of 8 cores, beating the current competition by two cores, offering competitive clock speeds and offer a much better power envelope. If this happens, the competition is in for some serious pummelling.
More secure than the competition
As outlined by AMD’s chief executive, Lisa Su, in January 2018, Zen 2 based processors will contain hardware mitigations for Spectre-like exploits. After swiftly providing micro-code updates for OS vendors, AMD is now the first x86 processor manufacturer to provide actual Spectre hardened hardware. Market-share leader Intel, did not provide an update when customers can expect a more secure processor.